1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the invention relates to a ferroelectric random access memory (FeRAM) having an error checking and correcting (ECC) circuit and using a ferroelectric capacitor.
2. Description of the Related Art
Attention has recently been attracted to a ferroelectric random access memory using a ferroelectric capacitor as a nonvolatile semiconductor memory device. The ferroelectric random access memory nonvolatilely stores binary data according to the amount of different two polarizations (amount of remanent polarization) of a ferroelectric using the fact that spontaneous polarization, one of characteristics of the ferroelectric exhibits a hysteresis characteristic.
The memory cells (unit cells) of a prior art FeRAM generally adopt the same architecture as those of a dynamic random access memory (DRAM). In the prior art FeRAM, a paraelectric capacitor of the DRAM is replaced with a ferroelectric capacitor and the ferroelectric capacitor is connected in series to a cell transistor to form a unit cell. Such unit cells are arranged two-dimensionally to configure a large-capacity memory cell array.
There are two types of FeRAM. One is a so-called 2T/2C FeRAM from which data is read using two unit cells, and the other is a so-called 1T/1C FeRAM from which data is read using one unit cell.
Data is read from an FeRAM by applying a voltage to a ferroelectric capacitor and reversing the polarization. In other words, the read of data from the FeRAM is destructive read. It is thus necessary to write back the read data. In general, the compared and amplified state of read data is maintained by a sense amplifier to write data “0.” Then, the potential of a plate line drops to VSS from the state to write data “1.” It is more effective to write data “0” first and then data “1” as a data write-back operation.
In the above destructive-read type FeRAM, data is repeatedly written each time data is read out. Particularly in an FeRAM with an ECC circuit, read data is written back in accordance with the results of error correction and correct data can be written. The ECC circuit can thus improve the reliability of the FeRAM.
However, it takes appropriate time to perform an error correcting operation in the ECC circuit. The following problem therefore occurs. When data is written back after its error is corrected, time required for writing back the data, including time required for correcting the error, is lengthened. In other words, when data is written back in accordance with the results of error correction in the ECC circuit, the results of error correction can be reflected in the data write-back operation, but cycle time is lengthened.
When data “0” is written first and then data “1” is done as a data write-back operation, the error correction in the ECC circuit has only to be completed at least by the end of writing of data “0” in order to reflect the results of the error correction. In other words, if time required for the error correction is shorter than that required for writing data “0,” the results of the error correction can be reflected in the writing of data “1” without lengthening cycle time. If, however, time required for the error correction is longer than that required for writing data “0,” the cycle time is lengthened accordingly.
As a technique related to the above, there is proposed a technique of improving the precision of detection of errors of data (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 11-16389).